Smartphone Building
Part · display

LTPO transistor backplane

Pattern a hybrid LTPS/oxide6T2C LTPO pixel/GOA array on one process glass with banks and final COG/FOG pad interfaces; independently test the bare array. Source-checked architectural correction; critical whole-node chemistry/interface research remains unresolved.

Discovered · unresearchedClosure: OpenInventory incomplete

Capability requirements and tolerances

Consumer-specific numerical targets, quantities and acceptance limits remain open or incompletely reviewed. No smartphone-grade suitability is claimed. Distinct capability tiers require their own making route and qualification.

Making steps · draft selected for navigation; not a validated fabrication specification.

Known Parts and Tools

The selected route supplies this page's inventory and the map's dependency links from one record. Further requirements may be missing; review flags do not prove physical suitability.

RequirementRoleUseRelationship status
Display substratePartincorporated once into moving bare backplaneCycle-checked; compatibility unknown
Interconnect deposition stockPartconsumed feedstockCycle-checked; compatibility unknown
Backplane dielectric stockPartconsumed feedstockCycle-checked; compatibility unknown
Oxide TFT target stockPartconsumed feedstockCycle-checked; compatibility unknown
Deposition equipmentToolreusedCycle-checked; compatibility unknown
Exposure equipmentToolreusedCycle-checked; compatibility unknown
Etching equipmentToolreusedCycle-checked; compatibility unknown
Mask making equipmentToolreusedCycle-checked; compatibility unknown
Heat treatment equipmentToolreusedCycle-checked; compatibility unknown
Vacuum systemsToolreusedCycle-checked; compatibility unknown
Gas handlingToolreusedCycle-checked; compatibility unknown
PhotoresistPartconsumedCycle-checked; compatibility unknown
Photoresist developerPartconsumedCycle-checked; compatibility unknown
Backplane test structuresPartconsumed verificationCycle-checked; compatibility unknown
Electrical instrumentsToolverificationCycle-checked; compatibility unknown
Optical instrumentsToolverificationCycle-checked; compatibility unknown
CleanroomToolreusedCycle-checked; compatibility unknown
Cleaning equipmentToolreused; reusedCycle-checked; compatibility unknown
Regulated powerToolreusedCycle-checked; compatibility unknown
Cooling systemsToolreusedCycle-checked; compatibility unknown
VentilationToolreused; reusedCycle-checked; compatibility unknown
Chemical protection equipmentToolreused; reusedCycle-checked; compatibility unknown
Chemical effluent collection equipmentToolreused; reusedCycle-checked; compatibility unknown
Display LTPS source chargePartconsumed deposited feedCycle-checked; compatibility unknown
Display LTPS crystallization moduleToolreusedCycle-checked; compatibility unknown
Display pixel planarization and bank chargePartconsumed deposited feedCycle-checked; compatibility unknown
Display interface and drive test fixtureToolverificationCycle-checked; compatibility unknown
Display film thickness test fixtureToolverificationCycle-checked; compatibility unknown
Display panel holderPartreusedCycle-checked; compatibility unknown
Process controllerToolreusedCycle-checked; compatibility unknown
Workshop computerToolreused physical hostCycle-checked; compatibility unknown
Programming cablePartreusedCycle-checked; compatibility unknown
Distribution cablePartreusedCycle-checked; compatibility unknown
Display process cleaning chargePartconsumed commissioning and operationCycle-checked; compatibility unknown
Clean handling carrierPartreusedCycle-checked; compatibility unknown
Dry storage coverToolreusedCycle-checked; compatibility unknown
Workshop surfacesToolreusedCycle-checked; compatibility unknown
ContainersToolreusedCycle-checked; compatibility unknown
Unselected candidate inventories · 1

These records expose known requirements and alternative or blocked hypotheses. They add no manufacturing links or selected discovery depth.

Deposit and pattern bottom-gate oxide TFT array on glass with passivation, storage capacitors and row/column driver interfaces

Method remains open.

Memory-first hypothesis; inventory and compatibility unreviewed.

Making outline

  1. Pattern a hybrid LTPS/oxide6T2C LTPO pixel/GOA array on one process glass with banks and final COG/FOG pad interfaces; independently test the bare array.
  2. One base glass travelsS0->S1->S2->S3->S4; second prefrittedlidL0 separate. Track actual source, installed pattern, transfer, calibration, controls and initial/recurring witness/service charges.
  3. No full research completion or physical/final material acceptance while B01-B03 remain.

What remains unresolved

Sources and leads

Source scope and research notes determine which claims have been checked. A URL does not establish a complete making route.

Proposed capability specification
{
  "function": "Pattern a hybrid LTPS/oxide6T2C LTPO pixel/GOA array on one process glass with banks and final COG/FOG pad interfaces; independently test the bare array.",
  "quantity": "One physical intermediate per attempted panel plus separately ledgered commissioning, reject, destructive, calibration and aging stock; final module count1.",
  "consumer_panel_contract": {
    "diagonal_mm": 157.48,
    "active_width_mm": 65.9932817866759,
    "active_height_mm": 142.9854438711311,
    "pixels": [
      1080,
      2340
    ],
    "logical_pixels": 2527200,
    "RGB_stripe_subpixels": 7581600,
    "pixel_pitch_um": 61.104890543218424,
    "RGB_stripe_horizontal_cell_um": 20.368296847739476,
    "refresh_modes_Hz": [
      1,
      60,
      120
    ],
    "RGB888_active_payload_bits_per_s": 7278336000,
    "source_lane_design": "4×2.5Gb/s candidate; timing/overhead/range not yet final",
    "module_budget_mm": [
      76,
      156,
      2.5
    ],
    "hole": "none; top-bezel camera",
    "touch": "separate laminated capacitive panel",
    "HDR_input": "10bpc RGB input; DSC1.2 at10bits/pixel (3:1), two540-pixel slices of20rows; fourD-PHY2.5Gb/sdata lanes",
    "DSC_slices": {
      "horizontal": 2,
      "width_px": 540,
      "height_rows": 20,
      "vertical_groups": 117
    },
    "compressed_active_payload_bits_per_s": 3032640000,
    "PHY": "fourD-PHY2.5Gb/sdata lanes plus differentialclock;actualPPS/timing/pinassignmentpendingcentralcontract",
    "peak": "Project2600cd/m2 at CTS1.2 8% center white plus2%APL background; explicitly no Samsung measurement transfer",
    "sustained": "Project >=600cd/m2 full-screen D65 for30min at25C and120Hz",
    "color": "Project100%sRGB and>=95%P3-D65 area coverage, meanDeltaE2000<=3; intersection coverage and exact patches proposed",
    "power": "Project panel and driver<=4W full-screen600nit120Hz,<=8W transient peak",
    "temperature": "Project panel operating surface<=45C at25C ambient",
    "lifetime": "Project LT95>=3000h at200nit full-screenD65,60Hz,25C, directly measured dedicated stock, no unsupported acceleration",
    "supply_interface": "Project 5.0V +/-5%, maximum2A; all internal rail generation is physical panel module hardware and included in4W/8W budgets"
  },
  "critical_immediate_blocks": [
    "B01: Fully named matched RGB transport/emitter/electrode/capping recipe and exact life/gamut/power grade unresolved after checked alternatives.",
    "B02: Actual paired LTPO pixel/bank/mask CAD, DSC/PPS/driver rails/pads and compensation timing contract remain unresolved.",
    "B03: Scope-specific material/process windows and independent calibration guardbands require B01/B02 and representative trials."
  ],
  "independent_acceptance": "Actual spectral/angular/DSC/film/package/all-rail thermal tests with independent references; no generic microscope/meter equivalence."
}
Earlier research provenance

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Used by

Items that directly require this item in their selected inventory.

Paths from Smartphone

These routes together include every item that can lead from Smartphone to this item. Repeated path combinations are collapsed; recipes are omitted.

Shortest route: Smartphone → Display panel → Display encapsulated intermediate → OLED-coated backplane → LTPO transistor backplane

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